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january 2010 doc id 16312 rev 1 1/12 AN3070 application note managing the driver enable signal for rs-485 and io-link communications with the stm32??s usart introduction rs-485 and io-link are half-duplex communic ation protocols that offer easy ways of implementing the physical layer in industrial networks. the stm32f10x, which comes with up to 5 uart interfaces and features fast dma transfer and low interrupt latency, meets the rs-485 and io-link timing specifications. this application note aims at providing timing measurements of the de signal (driver enable) switching by using two different methods for managing this signal in rs-485 and io-link master transmission. the application note is organized into three parts: it first explains why the timing of the de signal is critical it then describes the two methods used to manage the de signal and, finally, it gives different measurements of the de signal switching time www.st.com
contents AN3070 2/12 doc id 16312 rev 1 contents 1 de signal timing constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 description of the methods used to manage the de signal . . . . . . . . . 6 2.1 method using the dma interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 method using the usart interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 measuring the de signal switching time using the two methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 measuring the de signal switching time . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1.1 measuring the de signal switching time using the dma interrupt method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1.2 measuring the de signal switching time using the usart interrupt method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AN3070 list of tables doc id 16312 rev 1 3/12 list of tables table 1. timing measurements of de switching at 72 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2. timing measurements of de switching at 24 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. timing measurements of de switching at 72 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. timing measurements of de switching at 24 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 5. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
list of figures AN3070 4/12 doc id 16312 rev 1 list of figures figure 1. de timing constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. dma interrupt method to control the de signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. usart interrupt method to control the de signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. zoom in de signal switching period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
AN3070 de signal timing constraint doc id 16312 rev 1 5/12 1 de signal timing constraint for serial half-duplex communication protocols like rs-485 & io-link, the master needs to generate a direction signal to control the transceiver (phy). this signal informs the phy if it must act in send or receive mode. the timing of this control is critical, especia lly when switching from the send to the receive mode, as the application has to make sure that the device is in reception mode before data are sent by the other entity. the master has to free the tx/rx line in no more than a bit time, otherwise there is a collision with the slave response. so the de signal has to switch from hi gh to low level within the bit time that follows the last bit of the last byte sent by the master. figure 1. de timing constraint the master should be able to guarantee the timing of the de signal (imposed by the rs-485 & io-link specifications). the de signal is managed by a gpio. note that in this application note, the de signal is emulated by gpio port c pin 6 (pc6), however any gpio could be used. m as ter req u e s t s l a ve re s pon s e t bit t c/q line de (driver en ab le) a i17 3 56
description of the methods used to manage the de signal AN3070 6/12 doc id 16312 rev 1 2 description of the methods used to manage the de signal the purpose of this section is to provide two methods to control the de signal and switch between the usart send and receive modes. the first method uses two interrupts: the transmit complete interrupt of the dma and the transmit complete interrupt of the usart. the second method uses two usart interrupts: the transmit complete interrupt and the transmit buffer empty interrupt. 2.1 method using the dma interrupt in this method, the dma manages the data buffer transmission entirely. it continuously sends the data buffer to the usart data register until the dma counter reaches 0. when the dma transmit complete interrupt occurs, the usart transmit complete interrupt is enabled. in this interrupt, the de pin is driven low. the de signal goes high just before the dma transfer is enabled. figure 2 shows an example of management of the de signal by using the dma transmit complete interrupt. figure 2. dma interrupt method to control the de signal 2.2 method using the usart interrupt the transmit complete interrupt of the usart is used to drive low the de pin, and so inform the slave to send its response. the transmit data register empty interrupt is also used to drive this pin high to inform that the master is to send data to the slave. figure 3 shows an example of the de signal management using the usart interrupts. the de pin is pulled high before the first byte is sent. it is driven low after the last bit of the last byte is sent. this is done by enabling th e tc interrupt during the last byte transmission. the next occurrence of the transmit complete interrupt drives the de pin low. %nter$-! .o %nablethe53!244#interrupt $isablethe$-!4#interrupt #learthe$-!4#pendingbit 9es $-!transmit completeinterrupt occurred interrupt %xitinterrupt ai $rivelowthe$%pin $isablethe53!244#interrupt #learthe53!244#pendingbit %xitinterrupt %nter53!24 interrupt
AN3070 description of the methods used to manage the de signal doc id 16312 rev 1 7/12 figure 3. usart interrupt method to control the de signal %nter53!24 9es $rivethe$%pinlow .o (asthewhole databufferbeen transmitted interrupt %xitinterrupt 9es $isable4#interrupts #learthe4#pendingbit 9es $o thedatatobe transmittedcorrespondto thelastbyte .o 9es 48%flag 9es 48%flag )tisthefirstbyte drivethe$%pinhigh thensendthefirstbyte 3endthedatabyte .o ai 3endthelastdatabyte %nablethe4#interrupt $isablethe48%interrupt .o $o thedatatobe transmittedcorrespondto thefirstbyte .o )sitonlyone bytetobesent %nablethe4#interrupt $isablethe48%interrupt 9e s
measuring the de signal switching time using the two methods AN3070 8/12 doc id 16312 rev 1 3 measuring the de signal switching time using the two methods this section gives some de timing measurements using the two previously described methods. the timing to be measured is the time interval between the end of the stop bit of the last byte and the falling edge of the de signal. it is measured in cp u clock cycles (refer to figure 4 ). figure 4. zoom in de signal switching period the mco pin (pa8) is used to output the system clock (cpu clock) in order to measure in cpu cycles the time taken by the de signal to switch to the low level. the end of the stop bit is evaluated by measuring the number of cpu clock cycles during a bit time. this application note is released with two ex amples of firmware that implement the two previously described methods. both examples describe the same se q uence: drive pc6 high (de signal), send a buffer of 4 bytes and then drive pc6 low. the user can select the cpu fre q uency (72 mhz or 24 mhz) by commenting/uncommenting the following define in the main.c files: #define hclk_freq_72mhz 72 mhz is selected by default. 3.1 measuring the de signal switching time this timing depends on different factors such as the compiler used, the level of optimization or the cpu fre q uency. the examples are built with two compilers: keil? 4.00 and iar 5.40. they implement two optimization modes: low optimization and high optimization on timing. the baud rate for transmission is 230400 baud (bit time = 4.34 s), 1 stop bit. $% 48 3ystemclock-#/pin $%switchtimetobemeasured ,imitofthestopbit $%pinisdrivenlow ai
AN3070 measuring the de signal switching time using the two methods doc id 16312 rev 1 9/12 3.1.1 measuring the de signal sw itching time using the dma interrupt method ta bl e 1 gives the different timings measured at 72 mhz using the dma interrupt method. ta bl e 2 gives the different timings measured at 24 mhz using the dma interrupt method. 3.1.2 measuring the de signal sw itching time using th e usart interrupt method ta bl e 3 gives the different timings measured at 72 mhz using the usart interrupt method. ta bl e 4 gives the different timings measured at 24 mhz using the usart interrupt method. table 1. timing measurements of de switching at 72 mhz compiler number of cpu cycles iar 5.40 / keil 4.0 about 25 table 2. timing measurements of de switching at 24 mhz compiler number of cpu cycles iar 5.40 / keil 4.0 about 22 table 3. timing measurements of de switching at 72 mhz compiler number of cpu cycles iar 5.40 / keil 4.0 about 43 table 4. timing measurements of de switching at 24 mhz compiler number of cpu cycles iar 5.40 / keil 4.0 about 33
conclusion AN3070 10/12 doc id 16312 rev 1 4 conclusion this application note presents two methods for managing the de signal and guaranteeing the timing imposed by the rs-4 85 & io-link specifications: the first method uses the dma transmit complete interrupt and the usart transmit complete interrupt. it is easy to implement, and it leaves the cpu free to perform other tasks. the second method uses the usart interrupt. it does not re q uire the dma channel and so, can be implemented while the dma is not available becaused used for other purposes. compared to the usart interrupt method, the dma interrupt method achieves lower de signal switching times. so, if dma is available for data transmission, it is preferable to use it. the two methods meet the rs-485 & io-link timing re q uirement of 230 kbs transfer speed (bit time = 4.34 s).
AN3070 revision history doc id 16312 rev 1 11/12 5 revision history table 5. document revision history date revision changes 11-jan-2010 1 initial release.
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